Tradeoffs in Design of Low-Power Gated-Oscillator Clock and Data Recovery Circuits
نویسندگان
چکیده
منابع مشابه
Tradeoffs in Design of Low-Power Gated-Oscillator CDR Circuits
This article describes some techniques for implementing low-power clock and data recovery (CDR) circuits based on gated-oscillator (GO) topology for short distance applications. Here, the main tradeoffs in design of a high performance and power-efficient GO CDR are studied and based on that a top-down design methodology is introduced such that the jitter tolerance (JTOL) and frequency tolerance...
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ژورنال
عنوان ژورنال: Journal of Low Power Electronics
سال: 2007
ISSN: 1546-1998
DOI: 10.1166/jolpe.2007.145